The present invention relates to Joint Text Action Group (JTAG) ports generally.
Memory units are very common in many different types of products. All memory units are programmable but the types of memory units differ in whether or not and how they are erased. Read only memory (ROM) units are not erasable and require replacement if the information programmed therein must be changed. Erasable programmable, read only memory (EPROM) units use electrical signals to program them but require ultraviolet light to erase the entire chip at once. Electrically erasable programmable, read only memory (EEPROM) units and FLASH EEPROM units use electrical signals for erasing and for programming. Thus, a single bit or a single word can be changed if desired.
Included in the term xe2x80x9cmemory unitsxe2x80x9d are programmable logic devices (PLDs) which, instead of storing data as do memory units, store logical equations. A PLD can be based on any of the memory unit types.
To reprogram a programmable memory unit, the unit must be placed into a programming device which erases the unit in the appropriate manner and then electrically programs the unit. For memory units formed in a chip which is connected to a circuit board via a socket, this is not a problem since the units are typically removable from the socket.
However, those units which are directly soldered to the circuit board and those which are formed within a multi-function chip cannot be removed to the programming device. These units can be operated on (i.e. read, programmed, erased, verified, etc.) via a parallel port.
In-system programming (ISP) provides a method of operating on an on-chip memory unit, or any non-removable memory unit. IEEE Standard 1149.1 defines a test access port, known as a xe2x80x9cJTAG portxe2x80x9d, through which in-system programming occurs using a serial channel. FIG. 1, to which reference is now made, illustrates a personal computer (PC) 10 having a parallel port 11 which controls a memory chip 12 having a JTAG port 14 and a plurality of general ports 15.
In order to operate with a JTAG port, the memory chip 12 must also have a JTAG controller 16 which converts the serial data transmitted through the JTAG port 14 to the parallel format needed for accessing the memory unit, labeled 18, via a parallel bus 20. The bus can either be a single bus for data and address signals or two busses, one for data signals and one for address signals. In addition, the JTAG controller 16 decodes the instructions sent to into control signals for controlling the operation of the memory unit 18. These control signals are provided to the memory unit 18 via a control bus 29.
The JTAG port 14 has four pins, one each for the clock signal TCK, a control signal TMS, a data in signal TDI and a data out signal TDO. The data in signal TDI is a serial presentation of the data and address information to be provided to the memory unit 18 as well as of the instructions to the memory unit 18. JTAG controller 16 converts the received data to a parallel format for presentation to the memory unit 18. The parallel format includes data, address and instruction information.
Although not shown, the general ports 15 are also connected to PC 10 or to other devices on the board and are used for accessing the memory unit 18 and any other elements on the memory chip 12. In general, the general ports 15 are eight pin ports and are in steady use while the JTAG port 14 is only used when the data in the memory unit 18 must be changed.
An object of the present invention is to use a general port as a JTAG port.
Applicants have realized that there is no need for a separate, dedicated JTAG port. Instead, a part of a general, eight-pin port can be configured to accept the JTAG data and provide it to the JTAG controller 16.
There is therefore provided, in accordance with a preferred embodiment of the present invention, a memory chip which uses a multi-pin port as a JTAG port. The chip includes a JTAG controller, at least one internal block and a configuration unit which selectively configures four pins of one of the multi-pin ports of the chip to communicate JTAG data to the JTAG controller or to communicate non-JTAG data to the at least one internal block.
Additionally, in accordance with a preferred embodiment of the present invention, the configuration unit can be generally permanent or it can be modifiable. For example, the modifiable configuration unit can be a volatile memory (VM) configuration unit or a product term output of a programmable logic device (PLD).
Moreover, in accordance with a preferred embodiment of the present invention, the memory chip also includes a flip-flop for acquiring the output of the modifiable configuration unit and for providing the output to the selected multi-pin port, wherein a reset input of the flip-flop is connected to an output line of the JTAG controller.